In recent years, along with more size reduction and a higher mold rate of electronic devices, such as printers, an area of a metal housing with which the device is electromagnetically shielded has been reduced. Also, in a printed circuit board, with a higher-density package, a mounted component, such as an LSI, is more miniaturized, and its required voltage is decreased more. The reduction in area of the metal housing, the miniaturization of the LSI, and the decrease in voltage make higher the probability of malfunction of a device circuit due to exogenous noise, such as electrostatic discharge noise (hereafter referred to as “ESD noise”).
FIGS. 9A and 9B illustrate a configuration for preventing the malfunction caused by the ESD noise in a conventional multilayer printed circuit board 101. FIG. 9A is a plan view, and FIG. 9B is a perspective view. The multilayer printed circuit board 101 is disposed on a metal housing 117, and includes a first conductive layer 121 and a second conductive layer 122. A dielectric layer (not shown) is formed between the first conductive layer 121 and the second conductive layer 122.
In the first conductive layer 121, there are formed a first frame ground pattern (hereafter referred to as “first FG pattern”) 102 and a first signal ground pattern (hereafter referred to as “first SG pattern”) 103. The first FG pattern 102 and the first SG pattern 103 are separated from each other by a first slit portion 104. On the first FG pattern 102, there is mounted an external interface component 106, such as a connector or a switch. On the first SG pattern 103, there are mounted a first semiconductor device 107, a second semiconductor device 109, and a third semiconductor device 110. The external interface component 106 and the first semiconductor device 107 are connected to each other over the first slit portion 104 by a signal wiring 105. Further, the second semiconductor device 109 and the third semiconductor device 110 are connected to each other by a signal wiring 108. In FIGS. 9A and 9B, respective clearances defined between the signal wirings 105 and 108, and the first FG pattern 102 and the first SG pattern 103, are omitted.
Further, in the second conductive layer 122, a second frame ground pattern (hereafter referred to as “second FG pattern”) 118 and a second signal ground pattern (hereafter referred to as “second SG pattern”) 119 are formed so as to overlap with the first FG pattern 102 and the first SG pattern 103, respectively. The second FG pattern 118 and the second SG pattern 119 are separated from each other by a second slit portion 134.
The first FG pattern 102 and the second FG pattern 118 are short-circuited by conductive members 111 and 112. Further, the first SG pattern 103 and the second SG pattern 119 are short-circuited by conductive members 113, 114, 115, and 116. The conductive members 111, 112, 113, 114, 115, and 116 can be formed by through-holes or non-through via holes.
In the multilayer printed circuit board illustrated in FIGS. 9A and 9B, it is assumed that the ESD noise is applied to a neighborhood of the external interface component 106. The ESD noise flows into the first FG pattern 102, and also into the second FG pattern 118 from the first FG pattern 102. However, because the first and second FG patterns 102 and 118 are separated from the first and second SG patterns 103 and 119 by the first and second slit portions 104 and 134, respectively, the ESD noise hardly flows into the first and second SG patterns 103 and 119. Accordingly, in the multilayer printed circuit board 101, the semiconductor devices 109 and 110 that transfer a signal through the signal wiring 108 that does not extend over the slit are hardly affected by the ESD noise. Therefore, the semiconductor devices 109 and 110 are very high in resistance to the ESD noise.
However, when a high-speed signal flows in the signal wiring 105 connected to the external interface component 106 over the slit portion 104, a return current path of the high-speed signal is blocked by the first and second slit portions 104 and 134, resulting in a problem that radiation noise increases.
In order to solve the above-mentioned problem, there has been known a configuration disclosed in “EMC design of a printed circuit”, pages 134 to 136, written by Mark I. Montrose, published by Ohmsha, November, 1997. FIGS. 10A and 10B illustrate a multilayer printed circuit board having the configuration disclosed in this article, in which FIG. 10A is a plan view, and FIG. 10B is a perspective view. The same members as those in FIGS. 9A and 9B are denoted by identical symbols, and their description is omitted.
In the “EMC design of a printed circuit”, article, the second FG pattern 118 and the second SG pattern 119 of the second conductive layer 122 are connected to each other by a connecting member 120 having an electrical conductivity immediately below the signal wiring 105 extending over the first slit portion 104. The connecting member 120 enables the return current path to be ensured, which is formed when a current flows in the signal wiring 105 extending over the first slit portion 104, thereby suppressing the radiation noise.
In the configuration disclosed in the “EMC design of a printed circuit”, article, however, when the applied ESD noise flows into the second SG pattern 119 from the second FG pattern 118, the ESD noise is concentrated on the connecting member 120. Then, a magnetic field developed in the connecting member 120 is strongly bound to the signal wiring 105 extending over the first slit portion 104, thereby increasing a propagation quantity of the ESD noise to the signal wiring 105. As a result, a problem arises that a resistance to the ESD noise is deteriorated.